Electronic design automation (EDA) tools are applied extensively in the design of integrated circuits and in verification of these designs. EDA tools are used, for example, in logic synthesis, placement and routing of circuit elements, circuit layout and design rule checking. At the end of the design process, a set of reticles (also referred to as masks or templates) is generated for use in producing the integrated circuit (IC). Each reticle corresponds to one layer of the thin film structures that will be fabricated on a semiconductor wafer to produce the IC.
In the fabrication facility (fab), the reticles are used to print the successive circuit layers on the wafer in a photolithographic process. Each wafer undergoes hundreds of processing steps, including not only printing the reticles, but also material deposition, etching, cleaning and polishing. Defects in any of the process steps can substantially reduce the process yield. Therefore, monitoring tools are used to check wafers at nearly every step in the process to verify that the processing tools are functioning properly. Monitoring tools that are used for this purpose include systems for inspection and metrology of integrated circuit structures (typically optical or electron beam-based), as well as systems for electrical testing of circuit components. Reticles are also monitored for defects that may result in defects on the wafer. In the context of the present patent application and in the claims, the term “monitoring” should be understood as including all available modalities for testing wafers and reticles in production for purposes of detecting process or product defects. Monitoring modalities include, but are not limited to, measurement of critical dimensions (CD), film thickness and film composition; defect inspection, review and classification; electrical testing, including in-line and end-of-line tests; profilometry; ellipsometry; reflectometry; particle monitoring; and integrated defect detection and removal, using systems such as the Applied Materials “Bee.”
U.S. Pat. No. 6,529,621, whose disclosure is incorporated herein by reference, describes mechanisms for making and inspecting reticles, based on a reusable circuit design for use with EDA tools. The patent points out that conventional inspection systems waste valuable resources by inspecting some regions of the reticle too stringently, and not reliably inspecting other regions stringently enough. Conventional inspection systems and techniques are unable to distinguish between critical and non-critical areas of the reticle. The patent therefore describes mechanisms for flagging critical or noncritical regions of an IC pattern database. Other design flow procedures, such as reticle production and inspection and IC device fabrication, may then be based on the flagged critical or noncritical areas in the database.